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Language: Verilog
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OSCPU / yosys-sta
alexforencich / verilog-axi
Verilog AXI components for FPGA implementation
chipsalliance / yosys-f4pga-plugins
Plugins for Yosys developed as part of the F4PGA project.
analogdevicesinc / hdl
HDL libraries and projects
RapidSilicon / litex_reference_designs
Litex Reference Designs provides reference designs created out of IP Catalog using Litex integration capabilities.
siliconcompiler / lambdalib
Hardware abstraction library
IObundle / iob-cache
Verilog Configurable Cache
alexforencich / verilog-pcie
Verilog PCI express components
lnis-uofu / OpenFPGA
An Open-source FPGA IP Generator
ucb-bar / sha3
The-OpenROAD-Project / OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
T-head-Semi / openc910
OpenXuantie - OpenC910 Core
IObundle / iob-picorv32
IOb_SoC version of the Picorv32 RISC-V Verilog IP core